An integrated circuit memory may be formed of an assembly of memory elements, or memory cells, which may be arranged in an array. The writing and reading of data in memory cells are performed by dedicated logic circuits. A power supply generally provides the power necessary to the proper operation of the memory cell components and of the logic circuit. The memory power supply is generally obtained over one or several rails connected to all the memory cells and transmitting a power supply voltage. A memory is called volatile in the case where the data stored in the memory cells risk being lost when the memory power supply voltage falls below a minimum threshold.
FIG. 1 shows an example of a volatile memory cell 1 of a volatile memory of static random access memory type (SRAM). Memory cell 1 comprises six metal-oxide gate field-effect transistors, also called MOS transistors. Memory cell 1 belongs to a memory plane where the memory cells are distributed in rows and in columns.
Memory cell 1 comprises two inverters INVL, INVR connected in antiparallel. Inverters INVL, INVR are connected between a source of a high voltage VDD and a source of a low voltage, generally ground GND. In the following description, the ground voltage is selected to be equal to 0 V. Inverter INVL comprises a P-type MOS transistor PUL having its source connected to voltage source VDD and having its drain connected to a node IL corresponding to the input of inverter INVR. Inverter INVL comprises an N-type MOS transistor PDL having its source connected to ground GND and having its drain connected to node IL. Inverter INVR comprises a P-type MOS transistor PUR having its source connected to the source of voltage VDD and having its drain connected to a node IR corresponding to the input of inverter INVL. Inverter INVR comprises an N-type MOS transistor PDR having its source connected to ground GND and having its drain connected to node IR. The gates of transistors PUL and PDL are connected to node IR and the gates of transistors PUR and PDR are connected to node IL.
Nodes IL and IR are connected to bit lines BLT and BLF via switches PGL and PGR controlled by a row selection signal transmitted over a word line WL. Switch PGL may be an N-type MOS transistor having its gate connected to word line WL and having its other conduction terminals respectively connected to bit line BLT and to node IL. Similarly, switch PGR may be an N-type MOS transistor having its gate connected to word line WL and having its other conduction terminals respectively connected to node IR and to bit line BLF. Word line WL extends over the memory row comprising memory cell 1 and is connected to each memory cell in the row. Bit lines BLT and BLF extend on the memory column to which memory cell 1 belongs and are connected to each memory cell in the column.
In the following description, a bit line, a word line, or a node is said to be in the low state when the voltage on this line or on this node is at a low level, for example, at ground voltage GND, and a bit line, a word line, or a node is said to be in the high state when the voltage on this line or on this node is at a high level, for example, approximately equal to power supply voltage VDD. However, the high and low levels may be different for each word line, each bit line, and each node.
Memory cell 1 enables to store a binary datum or bit “0” or “1”. As an example, the storage of datum “1” corresponds to the case where the voltage at node IL is in the high state and the voltage at node IR is in the low state and the storage of datum “0” corresponds to the case where the voltage at node IL is in the low state and the voltage at node IR is in the high state.
There is a current tendency to increase the density of memories. This causes a local increase of the number of memory cells per column. However, some constraints may limit the maximum possible number of memory cells per column. One constraint is the capacitance of each bit line, which increases along with the number of memory cells coupled to the bit line. The larger the bit line capacitance, the more the bit line charge/discharge operation takes time during the read/write operation, which causes a decrease in the memory operating frequency.
U.S. Pat. No. 5,457,647 describes a RAM comprising a hierarchic configuration of bit lines wherein, for each column, bit lines BLT and BLF are divided into pairs of bit line portions. Each pair of bit line portions is connected to a group of memory cells. Two additional general bit lines are connected to all the pairs of bit line portions by switches. Selection lines extending along certain memory rows enable to select the switches. In a read or write operation, one of the pairs of bit line portions is selected by turning on the associated switches.
A hierarchic bit line configuration is complex since it entails the addition of general bit lines for each column, of switches distributed on each column, and of switch selection lines on certain memory rows.
For some applications, the consumption of the integrated circuit comprising a volatile memory is a critical factor. This may concern medical applications or wireless applications, which require a low consumption. As an example, the integrated circuit may be provided on medical implants, portable electronic elements, or a sensor network. It is, for example, an integrated circuit equipping a cell phone, the integrated circuit being powered by the phone battery.
A decrease of the memory consumption may be obtained by decreasing the memory power supply voltage. However, decreasing the power supply voltage results in decreasing the read current and accordingly decreasing the number of memory cells per column to avoid read errors in an operation of reading of the datum stored in memory cell 1.
Indeed, in an operation of reading of the datum stored in a memory cell, word line WL associated with the selected memory cell is set to the high state and the word lines of all the other memory rows are set to the low state. Switches PGL and PGR of the selected memory cell 1 are thus off. Bit lines BLT and BLF are left floating. According to the datum stored in the memory cell, the voltage of one of bit lines BLT, BLF rises and the voltage of the other bit line BLT, BLF decreases. However, even if switches PGL and PGR of all the other memory cells of the column are on, leakage currents may flow for these memory cells through some of switches PGL and PGR. With the decrease of power supply voltage VDD, the ratio of the read current (Tread) to the total leakage current corresponding to the sum of the leakage currents of the unselected memory cells (Ileakage) of the column decreases. Incorrect variations of the voltages of bit lines BLT and BLF, and thus read errors, may thus occur. It may then be necessary to decrease the number of memory cells per column.
The provision of additional bit lines dedicated to read operations to decrease leakage currents in read operations in a volatile memory of decreased consumption is known.
FIG. 2 shows an embodiment of a memory cell 2 such as that described in publication “A Large σVTH/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme” by Jui-Jen Wu, Yen-Huei Chen, Meng-Fan Chang, Po-Wei Chou, Chien-Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan-Hua Chu, Wen-Chin Wu, and Hiroyuki Yamauchi (IEEE Journal of Solid-State Circuits, Vol. 46, N°4, April 2011).
As compared with cell 1 shown in FIG. 1, memory cell 2 further comprises two read bit lines RBLT and RBLF, one read word line RWL, and two N-type MOS transistors, RPDL and RPDR, dedicated to read operations. The gate of transistor RPDL is connected to node IL. One of the conduction terminals of transistor RPDL is connected to read bit line RBLT and the other conduction terminal of transistor RPDL is connected to read word line RWL. The gate of transistor RPDR is connected to node IR. One of the conduction terminals of transistor RPDR is connected to read bit line RBLT and the other conduction terminal of transistor RPDR is connected to read word line RWL. Word line WL and bit lines BLT and BLF are dedicated to write operations.
In a read operation or a retention operation, read bit lines RBLT and RBLF are set to VDD.
In a read operation, read bit lines RBLT and RBLF are left floating and read word line RWL of the selected memory cell 2 is set to the low state while the word lines RWL associated with the other memory rows are maintained in the high state. Read bit lines RBLT and RBLF are initially floating in the high state. When datum “1” is stored in memory cell 2, only transistor RPDL is conductive. The voltage of bit line RBLT decreases. Transistor RPDR is off and bit line RBLF remains in the high state. Voltage difference Vdiff between bit lines RBLT and RBLF can then be detected. The time for which read word line RWL is set to the low state is sufficiently short for voltage Vdiff to remain smaller than the threshold voltage of transistors RPDL and RPDR. For the other memory cells of the column, the gate-source voltage of transistors RPDL and RPDR is at most equal to Vdiff. These transistors thus remain off. Further, the drain-source voltage of transistors RPDL and RPDR of the unselected memory cells of the column is at most equal to Vdiff so that leakage currents remain low as compared with those obtained for memory cell 1. Read errors are thus decreased even if the number of memory cells per column is high.
However, memory cell 2 shown in FIG. 2 has several disadvantages.
Indeed, for applications for which the memory cell power supply voltage is low, the on-state current of transistors RPDL or RPDR is decreased. The number of memory cells per column must then be decreased to decrease the impact of the read bit line capacitance during the read operation.
Further, even though transistors RPDL and RPDR may be designed to have decreased leakage currents in an operation of reading of the datum read from a memory cell of a column, the leakage currents of the unaddressed memory cells of the same column may disturb the read datum if the ratio of the read current (Tread) to the sum of the leakage currents (Ileakage) is too small, for example, smaller than 10.
Moreover, for applications where the memory must operate at a high rate, it may be necessary to decrease the number of cells per column to decrease the total duration of a read operation.
A memory cell overcoming all or part of the previously-described disadvantages is thus needed.